This invention relates to a programmable logic array arrangement, more particularly to a programmable logic array arrangement suitable for large scale logic integrated circuits (LSI).
Among prior art techniques of this type are included a master slice type LSI and a programmable logic array (PLA). According to the former technique it is possible to design and manufacture at low costs LSIs having various logic function by fabricating the LSIs with the same process steps up to the diffusion step and with various wiring masks. However, when this method is applied to the manufacture of larger scale logic integrated circuits, the design of the wiring masks becomes more troublesome so that this method is not economical.
For this reason, the latter method has been developed. According to this method, the layout of the electronic circuit elements and wirings required to construct such special logic circuits as a decoder, an AND array, an OR array, output buffer and the like is predetermined, and all logics are realized by individually designing only one mask to program cross points of an AND array and of an OR array for fabricating all types of logic LSIs according to a desired logic circuit. This method is described, for example, in an article of the title "Programmable Logic Arrays" of Dr. William N. Carr et al "MOS/LSI Design and Application" published by Mcgrow Hill Book Co., 1972, pages 229-257, chapter 8. This method, however, is defective in that the use of the chip area is redundant so that even if the manufacture of fine structure LSIs becomes possible by the development of the technique of manufacturing LSIs it would be impossible to realize high density and high efficiency logic LSIs but rather would result in the increase of redundancy.
Describing this defect in more detail, when designing logic circuits for various purposes, it has been impossible to fabricate desired logic circuits on the ground that, although AND arrays are formed abundantly, OR arrays are deficient or that OR arrays are surplus, but AND arrays are deficient. Furthermore, when constructing sequential circuits, it is necessary to separate the PLA output for applying it to the input of an external flip-flop circuit and to feedback the output of the flip-flop circuit to the PLA. To this end, it is necessary to provide an additional flip-flop circuit. When this flip-flop circuit is incorporated into the PLA, its efficiency of utilization would be degraded.